module Regfile (
    input   logic           clock,
    input  logic            reset,

    // Write Port
    input   logic           we,
    input   logic [4:0]     waddr,
    input   logic [63:0]    wdata,

    // Read Port 1
    input   logic [4:0]     raddr1,
    output  logic [63:0]    rdata1,

    // Read Port 2
    input   logic [4:0]     raddr2,
    output  logic [63:0]    rdata2
);
    logic [63:0]    gpr_array [31:0];

    import "DPI-C" function void dpic_set_gpr_ptr(input logic [63:0] a []);
    initial dpic_set_gpr_ptr(gpr_array);

    // Write
    always_ff @(posedge clock) begin
        if (reset) begin
            gpr_array[0] <= 64'b0;
        end
        else if (we && waddr != 5'h0) begin
            gpr_array[waddr] <= wdata;
        end
    end

    // Read
    assign rdata1 = gpr_array[raddr1];
    assign rdata2 = gpr_array[raddr2];

endmodule
